Switch networks are often used in data converters, such as digital-to-analog converters and analog-to-digital converters, to selectively connect resistors, currents and voltages within the converter based on values of individual bits of a digital word. In a common scenario, a single-pole, double-throw switch connects one terminal of resistor to either one of two different voltages, such as a reference voltage and ground, based on the value of a given bit. The single-pole, double-throw switch is typically implemented using a complimentary pair of MOS transistors, including an NMOS and a PMOS transistor, with sources and drains connected to the resistor terminal and the voltages, and gates connected to a complimentary pair of control signals derived from the corresponding digital bit.
One problem with these architectures is that, to preserve linearity and other performance metrics of the converter, the complimentary MOS switch transistors typically should each present the same “on” resistance, from source to drain, when activated to connect the resistor to the respective voltage. However, NMOS and PMOS transistors often inherently present different on resistances when driven under symmetrically similar conditions.
Prior efforts to force NMOS and PMOS switch transistors to present the same on resistance have resulted in relatively area- and power-inefficient circuits. Therefore, there exists a need for area- and power-efficient circuits to drive complimentary MOS switch transistors, in data converters and other circuits, in a manner to substantially equalize, or alternatively place into a predetermined relationship relative to each other, on resistances among these switch transistors.